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? semiconductor components industries, llc, 2006 july, 2006 ? rev. 11 1 publication order number: CS5156/d CS5156 cpu 5?bit nonsynchronous buck controller the CS5156 is a 5 ? bit nonsynchronous n ? channel buck controller. it is designed to provide unprecedented transient response for today?s demanding high ? density, high ? speed logic. the regulator operates using a proprietary control method, which allows a 100 ns response time to load transients. the CS5156 is designed to operate over a 4.25 ? 16 v range (v cc ) using 12 v to power the ic and 5.0 v as the main supply for conversion. the CS5156 is specifically designed to power pentium ? ii processors and other high performance core logic. it includes the following features: on board, 5 ? bit dac, short circuit protection, 1.0% output tolerance, v cc monitor, and programmable soft start capability. the CS5156 is backwards compatible with the 4 ? bit cs5151, allowing the mother board designer the capability of using either the cs5151 or the CS5156 with no change in layout. the CS5156 is available in 16 pin surface mount and dip packages. features ? n ? channel design ? excess of 1.0 mhz operation ? 100 ns transient response ? 5 ? bit dac ? backward compatible with 4 ? bit cs5150/cs5151 ? 30 ns gate rise/fall times ? 1.0% dac accuracy ? 5.0 v & 12 v operation ? remote sense ? programmable soft start ? lossless short circuit protection ? v cc monitor ? adaptive voltage positioning ? v 2 ? control topology ? current sharing ? overvoltage protection CS5156gdr16 http://onsemi.com a = assembly location wl, l = wafer lot yy, y = year ww, w = work week device package shipping ordering information CS5156gd16 so ? 16 48 units/rail so ? 16 2500 tape & reel soic ? 16 d suffix case 751b 1 16 dip ? 16 n suffix case 648 16 1 CS5156 awlyyww pin connections v cc1 v id3 lgnd v id2 comp v id1 v fb v id0 1 v cc2 v ffb v gate c off pgnd v id4 nc ss 1 CS5156 awlyww 16 marking diagrams 1 16 CS5156gn16 dip ? 16 25 units/rail
CS5156 http://onsemi.com 2 figure 1. application diagram, switching power supply for core logic ? pentium ii processor comp v ffb v fb v gate v cc2 v cc1 v id0 v id1 v id2 v id3 pgnd ss c off CS5156 aiei 12 v 330 pf 0.1 f lgnd 1200 f/16 v 3 0.1 f 1.3 v to 3.5 v @ 13 a v id0 v id1 v id2 v id3 aiei 1200 f/16 v 5 2.0 h irl3103 0.33 f 5.0 v mbr1535ct 3.3 k 100 pf v id4 v id4 2 1,3 absolute maximum ratings* rating value unit operating junction temperature, t j 0 to 150 c lead temperature soldering: wave solder (through hole styles only) (note 1) reflow: (smd styles only) (note 2) 260 peak 230 peak c storage temperature range, t s ? 65 to +150 c esd susceptibility (human body model) 2.0 kv 1. 10 second maximum. 2. 60 second maximum above 183 c. *the maximum package power dissipation must be observed. absolute maximum ratings pin name max operating voltage max current v cc1 16 v/ ? 0.3 v 25 ma dc/1.5 a peak v cc2 16 v/ ? 0.3 v 20 ma dc/1.5 a peak ss 6.0 v/ ? 0.3 v ? 100 a comp 6.0 v/ ? 0.3 v 200 a v fb 6.0 v/ ? 0.3 v ? 0.2 a c off 6.0 v/ ? 0.3 v ? 0.2 a v ffb 6.0 v/ ? 0.3 v ? 0.2 a v id0 ? v id4 6.0 v/ ? 0.3 v ? 50 a v gate 16 v/ ? 0.3 v 100 ma dc/1.5 a peak lgnd 0 v 25 ma pgnd 0 v 100 ma dc/1.5 a peak
CS5156 http://onsemi.com 3 electrical characteristics (0 c < t a < +70 c; 0 c < t j < +85 c; 8.0 v < v cc1 < 14 v; 5.0 v < v cc2 < 14 v; dac code: v id4 = v id2 = v id1 = v id0 = 1; v id3 = 0 ; cv gate = 1.0 nf; c off = 330 pf; c ss = 0.1 f, unless otherwise specified.) characteristic test conditions min typ max unit error amplifier v fb bias current v fb = 0 v ? 0.3 1.0 a open loop gain 1.25 v < v comp < 4.0 v; note 3 50 60 ? db unity gain bandwidth note 3 500 3000 ? khz comp sink current v comp = 1.5 v; v fb = 3.0 v; v ss > 2.0 v 0.4 2.5 8.0 ma comp source current v comp = 1.2 v; v fb = 2.7 v; v ss = 5.0 v 30 50 70 a comp clamp current v comp = 0 v; v fb = 2.7 v 0.4 1.0 1.6 ma comp high voltage v fb = 2.7 v; v ss = 5.0 v 4.0 4.3 5.0 v comp low voltage v fb = 3.0 v ? 160 600 mv psrr 8.0 v < v cc1 < 14 v @ 1.0 khz; note 3 60 85 ? db v cc1 monitor start threshold output switching 3.75 3.90 4.05 v stop threshold output not switching 3.70 3.85 4.00 v hysteresis start ? stop ? 50 ? mv v gate out source sat at 100 ma measure v cc2 ? v gate ? 1.2 2.0 v out sink sat at 100 ma measure v gate ? v pgnd ? 1.0 1.5 v out rise time 1.0 v < v gate < 9.0 v; v cc1 = v cc2 = 12 v ? 30 50 ns out fall time 9.0 v > v gate > 1.0 v; v cc1 = v cc2 = 12 v ? 30 50 ns shoot ? through current note 3 ? ? 50 ma v gate resistance resistor to lgnd. 20 50 100 k v gate schottky lgnd to v gate @ 10 ma ? 600 800 mv soft start (ss) charge time ? 1.6 3.3 5.0 ms pulse period ? 25 100 200 ms duty cycle (charge time /pulse period) 100 1.0 3.3 6.0 % comp clamp voltage v fb = 0 v; v ss = 0 0.50 0.95 1.10 v v ffb ss fault disable v gate = low 0.9 1.0 1.1 v high threshold ? ? 2.5 3.0 v pwm comparator transient response v ffb = 0 to 5.0 v to v gate = 9.0 v to 1.0 v; v cc1 = v cc2 = 12 v ? 100 125 ns v ffb bias current v ffb = 0 v ? 0.3 ? a 3. guaranteed by design, not 100% tested in production.
CS5156 http://onsemi.com 4 electrical characteristics (continued) (0 c < t a < +70 c; 0 c < t j < +85 c; 8.0 v < v cc1 < 14 v; 5.0 v < v cc2 < 14 v; dac code: v id4 = v id2 = v id1 = v id0 = 1; v id3 = 0 ; cv gate = 1.0 nf; c off = 330 pf; c ss = 0.1 f, unless otherwise specified.) characteristic unit max typ min test conditions dac input threshold v id0, v id1 , v id2 , v id3 , v id4 1.00 1.25 2.40 v input pull up resistance v id0, v id1 , v id2 , v id3 , v id4 25 50 100 k pull up voltage ? 4.85 5.00 5.15 v accuracy measure v fb = comp, 25 c t j 85 c ? ? 1.0 % v id4 v id3 v id2 v id1 v id0 0 1 1 1 1 ? 1.3266 1.3400 1.3534 v 0 1 1 1 0 ? 1.3761 1.3900 1.4039 v 0 1 1 0 1 ? 1.4256 1.4400 1.4544 v 0 1 1 0 0 ? 1.4751 1.4900 1.5049 v 0 1 0 1 1 ? 1.5246 1.5400 1.5554 v 0 1 0 1 0 ? 1.5741 1.5900 1.6059 v 0 1 0 0 1 ? 1.6236 1.6400 1.6564 v 0 1 0 0 0 ? 1.6731 1.6900 1.7069 v 0 0 1 1 1 ? 1.7226 1.7400 1.7574 v 0 0 1 1 0 ? 1.7721 1.7900 1.8079 v 0 0 1 0 1 ? 1.8216 1.8400 1.8584 v 0 0 1 0 0 ? 1.8711 1.8900 1.9089 v 0 0 0 1 1 ? 1.9206 1.9400 1.9594 v 0 0 0 1 0 ? 1.9701 1.9900 2.0099 v 0 0 0 0 1 ? 2.0196 2.0400 2.0604 v 0 0 0 0 0 ? 2.0691 2.0900 2.1109 v 1 1 1 1 1 ? 1.2315 1.2440 1.2564 v 1 1 1 1 0 ? 2.1186 2.1400 2.1614 v 1 1 1 0 1 ? 2.2176 2.2400 2.2624 v 1 1 1 0 0 ? 2.3166 2.3400 2.3634 v 1 1 0 1 1 ? 2.4156 2.4400 2.4644 v 1 1 0 1 0 ? 2.5146 2.5400 2.5654 v 1 1 0 0 1 ? 2.6136 2.6400 2.6664 v 1 1 0 0 0 ? 2.7126 2.7400 2.7674 v 1 0 1 1 1 ? 2.8116 2.8400 2.8684 v 1 0 1 1 0 ? 2.9106 2.9400 2.9694 v 1 0 1 0 1 ? 3.0096 3.0400 3.0704 v 1 0 1 0 0 ? 3.1086 3.1400 3.1714 v 1 0 0 1 1 ? 3.2076 3.2400 3.2724 v 1 0 0 1 0 ? 3.3066 3.3400 3.3734 v 1 0 0 0 1 ? 3.4056 3.4400 3.4744 v 1 0 0 0 0 ? 3.5046 3.5400 3.5754 v
CS5156 http://onsemi.com 5 electrical characteristics (continued) (0 c < t a < +70 c; 0 c < t j < +85 c; 8.0 v < v cc1 < 14 v; 5.0 v < v cc2 < 14 v; dac code: v id4 = v id2 = v id1 = v id0 = 1; v id3 = 0 ; cv gate = 1.0 nf; c off = 330 pf; c ss = 0.1 f, unless otherwise specified.) characteristic unit max typ min test conditions supply current i cc1 no switching ? 8.5 13.5 ma i cc2 no switching ? 1.6 3.0 ma operating i cc1 v fb = comp = v ffb ? 8.0 13 ma operating i cc2 v fb = comp = v ffb ? 2.0 5.0 ma c off normal charge time v ffb = 1.5 v; v ss = 5.0 v 1.0 1.6 2.2 s extension charge time v ss = v ffb = 0 5.0 8.0 11.0 s discharge current c off to 5.0 v; v fb > 1.0 v 5.0 ? ? ma time out timer time out time v fb = v comp ; v ffb = 2.0 v; record v gate pulse high duration 10 30 50 s fault mode duty cycle v ffb = 0v 35 50 65 % package pin description package pin # pin symbol function so ? 16, dip ? 16 1, 2, 3, 4, 6 v id0 ? v id4 voltage id dac input pins. these pins are internally pulled up to 5.0 v providing logic ones if left open. v id4 selects the dac range. when v id4 is high (logic one), the dac range is 2.14 v to 3.54 v with 100 mv increments. when v id4 is low (logic zero), the dac range is 1.34 v to 2.09 v with 50 mv increments. v id0 ? v id4 select the desired dac output voltage. leaving all 5 dac input pins open results in a dac output voltage of 1.244 v, allowing for adjustable output volt- age, using a traditional resistor divider. 5 ss soft start pin. a capacitor from this pin to lgnd in conjunction with internal 60 a current source provides soft start function for the controller. this pin disables fault detect function during soft start. when a fault is detected, the soft start capacitor is slowly discharged by internal 2.0 a current source setting the time out before trying to restart the ic. charge/discharge current ratio of 30 sets the duty cycle for the ic when the regulator output is shorted. 7 c off a capacitor from this pin to ground sets the time duration for the on board one shot, which is used for the constant off time architecture. 8 v ffb fast feedback connection to the pwm comparator. this pin is connected to the regulator output. the inner feedback loop terminates on time. 9 v cc2 boosted power for the gate driver. 10 v gate mosfet driver pin capable of 1.5 a peak switching current. 11 pgnd high current ground for the ic. the mosfet driver is referenced to this pin. input capacitor ground and the anode of the schottky diode should be tied to this pin. 12 nc no connection. 13 v cc1 input power for the ic. 14 lgnd signal ground for the ic. all control circuits are referenced to this pin. 15 comp error amplifier compensation pin. a capacitor to ground should be provided exter- nally to compensate the amplifier. 16 v fb error amplifier dc feedback input. this is the master voltage feedback which sets the output voltage. this pin can be connected directly to the output or a remote sense trace.
CS5156 http://onsemi.com 6 ? + ? + ? + v cc1 ss v id0 v id1 v id2 v id3 v ffb low comparator v ffb fast feedback lgnd slow feedback pwm comparator ss low comparator ss high comparator 5 bit dac v cc1 monitor comparator error amplifier v cc2 c off v gate fault fault fault latch pgnd r s q q r s q q r s q latch pmw c off one shot off ? time timeout time ? out timer edge triggered extended off ? time timeout normal off ? time timeout maximum on ? time timeout (30 s) gate = on gate = off 2.0 a 60 a 5.0 v 0.7 v 2.5 v 1.0 v ? + ? + + ? 3.90 v 3.85v v fb comp figure 2. block diagram pwm comp v id4 applications information theory of operation v 2 control method the v 2 method of control uses a ramp signal that is generated by the esr of the output capacitors. this ramp is proportional to the ac current through the main inductor and is offset by the value of the dc output voltage. this control scheme inherently compensates for variation in either line or load conditions, since the ramp signal is generated from the output voltage itself. this control scheme inherently compensates for variation in either line or load conditions, since the ramp signal is generated from the output voltage itself. this control scheme differs from traditional techniques such as voltage mode, which generates an artificial ramp, and current mode, which generates a ramp from inductor current. figure 3. v 2 control diagram comp v ffb reference voltage + + pwm comparator ramp signal error amplifier error signal output voltage feedback v fb v gate e c ? ?
CS5156 http://onsemi.com 7 the v 2 control method is illustrated in figure 3. the output voltage is used to generate both the error signal and the ramp signal. since the ramp signal is simply the output voltage, it is af fected by any change in the output regardless of the origin of that change. the ramp signal also contains the dc portion of the output voltage, which allows the control circuit to drive the main switch to 0% or 100% duty cycle as required. a change in line voltage changes the current ramp in the inductor, affecting the ramp signal, which causes the v 2 control scheme to compensate the duty cycle. since the change in inductor current modifies the ramp signal, as in current mode control, the v 2 control scheme has the same advantages in line transient response. a change in load current will have an affect on the output voltage, altering the ramp signal. a load step immediately changes the state of the comparator output, which controls the main switch. load transient response is determined only by the comparator response time and the transition speed of the main switch. the reaction time to an output load step has no relation to the crossover frequency of the error signal loop, as in traditional control methods. the error signal loop can have a low crossover frequency, since transient response is handled by the ramp signal loop. the main purpose of this ?slow? feedback loop is to provide dc accuracy. noise immunity is significantly improved, since the error amplifier bandwidth can be rolled off at a low frequency. enhanced noise immunity improves remote sensing of the output voltage, since the noise associated with long feedback traces can be effectively filtered. line and load regulation are drastically improved because there are two independent voltage loops. a voltage mode controller relies on a change in the error signal to compensate for a deviation in either line or load voltage. this change in the error signal causes the output voltage to change corresponding to the gain of the error amplifier, which is normally specified as line and load regulation. a current mode controller maintains fixed error signal under deviation in the line voltage, since the slope of the ramp signal changes, but still relies on a change in the error signal for a deviation in load. the v 2 method of control maintains a fixed error signal for both line and load variation, since the ramp signal is affected by both line and load. constant off time to maximize transient response, the CS5156 uses a constant off time method to control the rate of output pulses. during normal operation, the off time of the high side switch is terminated after a fixed period, set by the c off capacitor. to maintain regulation, the v 2 control loop varies switch on time. the pwm comparator monitors the output voltage ramp, and terminates the switch on time. constant off time provides a number of advantages. switch duty cycle can be adjusted from 0 to 100% on a pulse by pulse basis when responding to transient conditions. both 0% and 100% duty cycle operation can be maintained for extended periods of time in response to load or line transients. pwm slope compensation to avoid sub ? harmonic oscillations at high duty cycles is avoided. switch on time is limited by an internal 30 s timer, minimizing stress to the power components. programmable output the CS5156 is designed to provide two methods for programming the output voltage of the power supply. a five bit on board digital to analog converter (dac) is used to program the output voltage within two different ranges. the first range is 2.14 v to 3.54 v in 100 mv steps, the second is 1.34 v to 2.09 v in 50 mv steps, depending on the digital input code. if all five bits are left open, the CS5156 enters adjust mode. in adjust mode, the designer can choose any output voltage by using resistor divider feedback to the v fb and v ffb pins, as in traditional controllers. the CS5156 is specifically designed to be backwards compatible with the cs5151, which uses a four bit dac code. start up until the voltage on the v cc1 supply pin exceeds the 3.9 v monitor threshold, the soft start and gate pins are held low. the fault latch is reset (no fault condition). the output of the error amplifier (comp) is pulled up to 1.0 v by the comparator clamp. when the v cc1 pin exceeds the monitor threshold, the gate output is activated, and the soft start capacitor begins charging. the gate output will remain on, enabling the nfet switch, until terminated by either the pwm comparator, or the maximum on time timer. if the maximum on time is exceeded before the regulator output voltage achieves the 1.0 v level, the pulse is terminated. the gate pin drives low for the duration of the extended off time. this time is set by the time out timer and is approximately equal to the maximum on time, resulting in a 50% duty cycle. then, the gate pin will drive high, and the cycle repeats. when regulator output voltage achieves the 1.0 v level present at the comp pin, regulation has been achieved and normal off time will ensue. the pwm comparator terminates the switch on time, with off time set by the c off capacitor. the v 2 control loop will adjust switch duty cycle as required to ensure the regulator output voltage tracks the output of the error amplifier. the soft start and comp capacitors will charge to their final levels, providing a controlled turn on of the regulator output. regulator turn on time is determined by the comp capacitor charging to its final value. its voltage is limited by
CS5156 http://onsemi.com 8 the soft start comp clamp and the voltage on the soft start pin (see figures 4 and 5). figure 4. CS5156 demonstration board startup in response to increasing 12 v and 5.0 v input voltages. extended off time is follo wed by normal off time operation when output voltage achieves regulation to the error amplifier output. m 250 s trace 3 ? 12 v input (v cc1 and v cc2 ) (5.0 v/div.) trace 1 ? regulator output voltage (1.0 v/div.) trace 4 ? 5.0 v input (1.0 v/div.) trace 2 ? inductor switching node (2.0 v/div.) figure 5. CS5156 demonstration board startup waveforms m 2.50 ms trace 3 ? comp pin (error amplifier output) (1.0 v/div.) trace 1 ? regulator output voltage (1.0 v/div.) trace 4 ? soft start pin (2.0 v/div.) if the input voltage rises quickly, or the regulator output is enabled externally, output voltage will increase to the level set by the error amplifier output more rapidly, usually within a couple of cycles (see figure 6). figure 6. CS5156 demonstration board enable startup waveforms m 10.0 s trace 1 ? regulator output voltage (5.0 v/div.) trace 2 ? inductor switching node (5.0 v/div.) normal operation during normal operation, switch of f time is constant and set by the c off capacitor. switch on time is adjusted by the v 2 control loop to maintain regulation. this results in changes in regulator switching frequency, duty cycle, and output ripple in response to changes in load and line. output voltage ripple will be determined by inductor ripple current working into the esr of the output capacitors (see figures 7 and 8). figure 7. peak ? to ? peak ripple on v out = 2.8 v, i out = 0.5 a (light load) m 1.00 s trace 1 ? regulator output voltage (10 mv/div.) trace 2 ? inductor switching node (5.0 v/div.)
CS5156 http://onsemi.com 9 figure 8. peak ? to ? peak ripple on v out = 2.8 v, i out = 13 a (heavy load) m 1.00 s trace 1 ? regulator output voltage (10 mv/div.) trace 2 ? inductor switching node (5.0 v/div.) transient response the CS5156 v 2 control loop?s 100 ns reaction time provides unprecedented transient response to changes in input voltage or output current. pulse by pulse adjustment of duty cycle is provided to quickly ramp the inductor current to the required level. since the inductor current cannot be changed instantaneously, regulation is maintained by the output capacitor(s) during the time required to slew the inductor current. overall load transient response is further improved through a feature called ?adaptive voltage positioning?. this technique pre ? positions the output capacitor?s voltage to reduce total output voltage excursions during changes in load. holding tolerance to 1.0% allows the error amplifier?s reference voltage to be targeted +40 mv high without compromising dc accuracy. a ?droop resistor?, implemented through a pc board trace, connects the error amplifier?s feedback pin (v fb ) to the output capacitors and load and carries the output current. with no load, there is no dc drop across this resistor, producing an output voltage tracking the error amplifier?s, including the +40 mv offset. when the full load current is delivered, an 80 mv drop is developed across this resistor. this results in output voltage being offset ? 40 mv low. the result of adaptive voltage positioning is that additional margin is provided for a load transient before reaching the ou tput voltage specification limits. when load current suddenly increases from its minimum level, the output capacitor is pre ? positioned +40 mv. conversely, when load current suddenly decreases from its maximum level, the output capacitor is pre ? positioned ? 40 mv (see figures 9, 10, and 11). for best transient response, a combination of a number of high frequency and bulk output capacitors are usually used. if the maximum on time is exceeded while responding to a sudden increase in load current, a normal off time occurs to prevent saturation of the output inductor. figure 9. CS5156 demonstration board response to a 0.5 to 13 a load pulse (output set for 2.8 v) trace 2 ? regulator output voltage (20 v/div.) trace 1 ? regulator output voltage (1.0 v/div.) figure 10. CS5156 demonstration board response to 13 a load turn on (output set for 2.8 v). upon completing a normal off time, the v 2 control loop immediately connects the inductor to the input voltage, providing 100% duty cycle. regulation is achieved in less than 20 s trace 1 ? regulator output voltage (1.0 v/div.) trace 2 ? inductor switching node (5.0 v/div.) trace 3 ? output current (0.5 to 13 amps) (20 v/div.)
CS5156 http://onsemi.com 10 figure 11. CS5156 demonstration board response to 13 a load turn off (output set for 2.8 v). v 2 control topology immediately connects inductor to ground, providing 0% duty cycle. regulation is achieved in less than 10 s trace 3 ? output current (13 to 0,5 amps) (20 mv/div.) trace 2 ? inductor switching node (5.0 v/div.) trace 1 ? regulator output voltage (1.0 v/div.) protection and monitoring features v cc1 monitor to maintain predictable startup and shutdown characteristics an internal v cc1 monitor circuit is used to prevent the part from operating below 3.75 v minimum startup. the v cc1 monitor comparator provides hysteresis and guarantees a 3.70 v minimum shutdown threshold. short circuit protection a lossless hiccup mode short circuit protection feature is provided, requiring only the soft start capacitor to implement. if a shor t circuit cond ition occurs (v ffb < 1.0 v), the v ffb low comparator sets the fault latch. this causes the mosfet to shut off, disconnecting the regulator from it?s input voltage. the soft start capacitor is then slowly discharged by a 2.0 a current source until it reaches it?s lower 0.7 v threshold. the regulator will then attempt to restart normally, operating in it?s extended off time mode with a 50% duty cycle, while the soft start capacitor is charged with a 60 a charge current. if the short circuit condition persists, the regulator output will not achieve the 1.0 v low v ffb comparator threshold before the soft start capacitor is charged to it?s upper 2.5 v threshold. if this happens the cycle will repeat itself until the short is removed. the soft start charge/discharge current ratio sets the duty cycle for the pulses (2.0 a/60 a = 3.3%), while actual duty cycle is half that due to the extended off time mode (1.65%). this protection feature results in less stress to the regulator components, input power supply, and pc board traces than occurs with constant current limit protection (see figures 12 and 13). if the short circuit condition is removed, output voltage will rise above the 1.0 v level, preventing the fault latch from being set, allowing normal operation to resume. figure 12. CS5156 demonstration board hiccup mode short circuit protection. gate pulses are delivered while the soft start capacitor charges, and cease during discharge m 25.0 ms trace 3 ? soft start timing capacitor (1.0 v/div.) trace 4 ? 5.0 v supply voltage (2.0 v/div.) trace 2 ? inductor switching node (2.0 v/div.) figure 13. startup with regulator output shorted m 50.0 s trace 4 ? 5.0 v from pc power supply (2.0 v/div.) trace 2 ? inductor switching node (2.0 v/div.) overvoltage protection overvoltage protection (ovp) is provided as result of the normal operation of the v 2 control topology and requires no additional external components. the control loop responds to an overvoltage condition within 100 ns, causing the top mosfet to shut off, disconnecting the regulator from it?s input voltage. external output enable circuit on/off control of the regulator can be implemented through the addition of two additional discrete components
CS5156 http://onsemi.com 11 (see figure 14). this circuit operates by pulling the soft start pin high, and the v ffb pin low, emulating a short circuit condition. figure 14. implementing shutdown with the CS5156 shutdown input 5.0 v mmun2111t1 (sot ? 23) 5 8 v ffb ss in4148 CS5156 external power good circuit an optional power good signal can be generated through the use of four additional external components (see figure 15). the threshold voltage of the power good signal can be adjusted per the following equation: v power good (r1 r2) 0.65 v r2 this circuit provides an open collector output that drives the power good output to ground for regulator voltages less than v power good . figure 15. implementing power good with the cs 5156 5.0 v power good 10 k v out pn3904 6.2 k r1 r2 pn3904 10 k r3 CS5156 figure 16. CS5156 demonstration board during power up. power good signal is activated when output voltage reaches 1.70 v. m 2.50 ms trace 4 ? 5.0 v input (2.0 v/div.) trace 3 ? 12 v input (v cc1 ) and (v cc2 ) (10 v/div.) trace 1 ? regulator output voltage (1.0 v/div.) trace 2 ? power good signal (2.0 v/div.) selecting external components the CS5156 can be used with a wide range of external power components to optimize the cost and performance of a particular design. the following information can be used as general guidelines to assist in their selection. nfet power transistors both logic level and standard mosfets can be used. the reference designs derive gate drive from the 12 v supply which is generally available in most computer systems and use logic level mosfets. a charge pump may be easily implemented to support 5.0 v only systems. multiple mosfets may be paralleled to reduce losses and improve efficiency and thermal management. voltage applied to the mosfet gates depends on the application circuit used. the gate driver output is specified to drive to within 1.5 v of ground when in the low state and to within 2.0 v of its bias supply when in the high state. in practice, the mosfet gates will be driven rail to rail due to overshoot caused by the capacitive load they present to the controller ic. for the typical application where v cc1 = v cc2 = 12 v and 5.0 v is used as the source for the regulator output current, the following gate drive is provided; v gate(h) 12 v 5.0 v 7.0 v (see figure 17.)
CS5156 http://onsemi.com 12 figure 17. CS5156 gate drive waveforms depicting rail to rail swing m 1.00 s m1 = v gate ? 5.0 v in channel 3 = v gate channel 2 ? inductor switching node the most important aspect of mosfet performance is rds on , which effects regulator efficiency and mosfet thermal management requirements. the power dissipated by the mosfets and the schottky diode may be estimated as follows; switching mosfet: power i load 2 rds on duty cycle schottky diode: power v forward i load ( 1 duty cycle ) duty cycle = v out v forward v in v forward (i load rds on of synch fet ) off time capacitor (c off ) the c off timing capacitor sets the regulator off time: t off c off 4848.5 when the v ffb pin is less than 1.0 v, the current char ging the c off capacitor is reduced. the extended off time can be calculated as follows: t off c off 24, 242.5 off time will be determined by either the t off time, or the time out timer, whichever is longer. the preceding equations for duty cycle can also be used to calculate the regulator switching frequency and select the c off timing capacitor: c off perioid ( 1 duty cycle ) 4848.5 where: period 1 switching frequency ?droop? resistor for adaptive voltage positioning adaptive voltage positioning is used to reduce output voltage excursions during abrupt changes in load current. regulator output voltage is offset +40 mv when the regulator is unloaded, and ? 40 mv at full load. this results in increased margin before encountering minimum and maximum transient voltage limits, allowing use of less capacitance on the regulator output (see figure 9). to implement adaptive voltage positioning, a ?droop? resistor must be connected between the output inductor and output capacitors and load. this is normally implemented by a pc board trace of the following value: r droop 80 mv i max adaptive voltage positioning can be disabled for improved dc regulation by connecting the v fb pin directly to the load using a separate, non ? load current carrying circuit trace. input and output capacitors these components must be selected and placed carefully to yield optimal results. capacitors should be chosen to provide acceptable ripple on the input supply lines and regulator output voltage. key specifications for input capacitors are their ripple rating, while esr is important for output capacitors. for best transient response, a combination of low value/high frequency and bulk capacitors placed close to the load will be required. output inductor the inductor should be selected based on its inductance, current capability, and dc resistance. increasing the inductor value will decrease output voltage ripple, but degrade transient response. thermal management thermal considerations for power mosfets and diodes in order to maintain good reliability, the junction temperature of the semiconductor components should be kept to a maximum of 150 c or lower. the thermal impedance (junction to ambient) required to meet this requirement can be calculated as follows: thermal impedance t junction(max) t ambient power a heatsink may be added to to ? 220 components to reduce their thermal impedance. a number of pc board layout techniques such as thermal vias and additional copper foil area can be used to improve the power handling capability of surface mount components. emi management as a consequence of large currents being turned on and off at high frequency, switching regulators generate noise as a consequence of their normal operation. when designing for compliance with emi/emc regulations, additional components may be added to reduce noise emissions. these components are not required for regulator operation and experimental results may allow them to be eliminated. the input filter inductor may not be required because bulk filter
CS5156 http://onsemi.com 13 and bypass capacitors, as well as other loads located on the board will tend to reduce regulator di/dt effects on the circuit board and input power supply. placement of the power component to minimize routing distance will also help to reduce emissions. figure 18. filter components 1000 pf 33 2.0 h figure 19. input filter 1200 pf 3.0/16 v 2.0 h + layout guidelines 1. place 12 v filter capacitor next to the ic and connect capacitor ground to pin 11 (pgnd). 2. connect pin 11 (pgnd) with a separate trace to the ground terminals of the 5.0 v input capacitors. 3. place fast feedback filter capacitor next to pin 8 (v ffb ) and connect it?s ground terminal with a separate, wide trace directly to pin 14 (lgnd). 4. connect the ground terminals of the compensation capacitor directly to the ground of the fast feedback filter capacitor to prevent common mode noise from effecting the pwm comparator. 5. place the output filter capacitor(s) as close to the load as possible and connect the ground terminal to pin 14 (lgnd). 6. to implement adaptive voltage positioning, connect both slow and fast feedback pins 16 (v fb ) and 8 (v ffb ) to the regulator output right at the inductor terminal. connect inductor to the output capacitors via a trace with the following resistance: r trace 80 mv i max this causes the output voltage to be +40 mv with no load, and ? 40 mv with a full load, improving regulator transient response. this trace must be wide enough to carry the full output current. (typical trace is 1.0 inch long, 0.17 inch wide). care should be taken to minimize any additional losses after the feedback connection point to maximize regulation. 7. if dc regulation is to be optimized (at the expense of degraded transient regulation), adaptive voltage positioning can be disabled by connecting to v fb pin directly to the load with a separate trace (remote sense). 8. place 5.0 v input capacitors close to the switching mosfet. route gate drive signals v gate (pin 10) with a trace that is a minimum of 0.025 inches wide. figure 20. layout guidelines to the negative terminal of the output capacitors v cc 100 pf 0.1 f soft start off time v comp to the negative terminal of the input capacitors 15 11 5 8 v ffb 1.0 f
CS5156 http://onsemi.com 14 figure 21. additional application diagram, 5.0 v to 3.3 v/10 a converter comp v ffb v fb v gate v cc2 v cc1 v id0 v id1 v id2 v id3 pgnd ss c off CS5156 si4410dy tantalum tantalum 3.3 v/10 a 5.0v 0.1 f 330 pf 0.1 f 0.33 f lgnd 100 pf 3.3 k 100 f/10 v 3 1.0 f mbrs120 mbrs120 100 f/10 v 3 1.0 f mbrs 120 3.0 h + + mbr1535ct 2 1,3 v id4 comp v ffb v fb v gate v cc2 v cc1 v id0 v id1 v id2 v id3 pgnd ss c off CS5156 3.3 v 330 pf 0.1 f lgnd 33 f/25 v 3 0.33 f 3.3 k si9410 0.1 f 12 v 5.0 h 2.5 v/7.0 a tantalum 100 f/10 v 2 figure 22. additional application diagram, 3.3 v to 2.5 v/7.0 a converter with 12 v bias 1.0 f mbr1535ct + + 100 pf tantalum 2 1,3 v id4
CS5156 http://onsemi.com 15 figure 23. additional application diagram, 5.0 v to 3.3 v/10 a converter with current sharing comp v ffb v fb v gate v cc2 v cc1 v id0 v id1 v id2 v id3 pgnd ss c off CS5156 si4410 tantalum tantalum 3.3 v/10 a 10 5.0v 0.1 f 330 pf 0.1 f 0.33 f lgnd 100 pf 3.3 k 100 f/10 v 3 connect to other circuits for current sharing 1.0 f mbrs120 mbrs120 100 f/10 v 3 1.0 f remote sense mbrs 120 3.0 h mbr1535ct + + v id4 2 1,3
CS5156 http://onsemi.com 16 package dimensions notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. 18 16 9 seating plane f j m r x 45 g 8 pl p ? b ? ? a ? m 0.25 (0.010) b s ? t ? d k c 16 pl s b m 0.25 (0.010) a s t dim min max min max inches millimeters a 9.80 10.00 0.386 0.393 b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.054 0.068 d 0.35 0.49 0.014 0.019 f 0.40 1.25 0.016 0.049 g 1.27 bsc 0.050 bsc j 0.19 0.25 0.008 0.009 k 0.10 0.25 0.004 0.009 m 0 7 0 7 p 5.80 6.20 0.229 0.244 r 0.25 0.50 0.010 0.019 so ? 16 d suffix case 751b ? 05 issue j dip ? 16 n suffix case 648 ? 08 issue r notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. dimension l to center of leads when formed parallel. 4. dimension b does not include mold flash. 5. rounded corners optional. ? a ? b f c s h g d j l m 16 pl seating 18 9 16 k plane ? t ? m a m 0.25 (0.010) t dim min max min max millimeters inches a 0.740 0.770 18.80 19.55 b 0.250 0.270 6.35 6.85 c 0.145 0.175 3.69 4.44 d 0.015 0.021 0.39 0.53 f 0.040 0.70 1.02 1.77 g 0.100 bsc 2.54 bsc h 0.050 bsc 1.27 bsc j 0.008 0.015 0.21 0.38 k 0.110 0.130 2.80 3.30 l 0.295 0.305 7.50 7.74 m 0 10 0 10 s 0.020 0.040 0.51 1.01 package thermal data parameter 16 ? so dip ? 16 unit r jc typical 28 42 c/w r ja typical 115 80 c/w
CS5156 http://onsemi.com 17 on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5773 ? 3850 CS5156/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative v 2 is a trademark of switch power, inc. pentium is a registered trademark of intel corporation.

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